1. Field of the Invention
The invention relates to bipolar transistors and, more particularly, to a method of forming a bipolar transistor with a self-aligned raised extrinsic base.
2. Description of the Related Art
Both non-self aligned and self-aligned bipolar transistors having a silicon (Si) or silicon-germanium (SiGe) intrinsic base and a doped polycrystalline silicon raised extrinsic base are the focus of integrated circuits fabricated for high performance mixed signal applications. Referring to FIG. 1, a non-self aligned bipolar transistor 10 with a polysilicon raised extrinsic base 11 can be formed by forming an emitter opening using a reactive ion etching (RIE) process through an oxide 13/polysilicon base layer 11 and stopping on a dielectric etch stop pad 14 (e.g., an oxide pad). The dielectric etch stop pad 14 is formed and defined with a lithography step prior to the deposition of the oxide 13/polysilicon 11 stack. However, this method results in a non-self aligned transistor structure 10 with limited performance. Specifically, the maximum oscillation frequency (fmax) for such a non-self aligned bipolar transistor structure 10 is low due to high base resistance (Rb). High Rb is caused by the large, non-self aligned, spacing 16 between the edge of the emitter 15 and the edge of the extrinsic base 11, which increases the current path and thus, the resistance between the emitter and the extrinsic base and which also significantly limits the electrical contact area 26 available between the intrinsic base 17 and the extrinsic base 11. As illustrated in FIG. 1, this spacing 16 is determined by the dielectric etch stop pad 14 dimension, which needs to be larger than the dimension of the emitter 15 opening due lithography alignment tolerance. As can also be seen from FIG. 1, such limited lithography tolerance leads to non-symmetric portions of the dielectric etch stop pad 14 around the emitter 15.
The maximum oscillation frequency of modern bipolar transistors has been increased by using a self-aligned structure that reduces the spacing between the emitter and the extrinsic base edges. A bipolar transistor with a self-aligned base incorporates the use of spacers in order to symmetrically place the emitter and extrinsic base edges within close proximity (e.g., see Jagannathan, et. al., “Self-aligned SiGe NPN transistors with 285 GHz fmax and 207 GHz fT in a manufacturable technology”, IEEE Electron Device Letters 23, 258 (2002) and J. S. Rieh, et. al., “SiGe HBTs with cut-off frequency of 350 GHz”, International Electron Device Meeting Technical Digest, 771 (2002)). In one method chemical mechanical polishing (CMP) is used to planarize the extrinsic base polysilicon over a pre-defined sacrificial emitter pedestal (e.g., see U.S. Pat. No. 5,128,271, Bronner et al., Jul. 7, 1992 (incorporated herein by reference), U.S. Pat. No. 6,346,453, Kovacic et al., Feb. 12, 2002 (incorporated herein by reference) and U.S Patent Application Pub. No. US2003/0057458 A1, Freeman et al., Mar. 27, 2003 (incorporated herein by reference)). An extrinsic base region formed in this manner has an area A and depth D with a low aspect ratio (D/A<<1). This low aspect ratio can lead to a significant difference in the extrinsic base layer thickness between small and large, as well as isolated versus nested, devices due to dishing caused by the CMP. In another method the intrinsic base is grown using selective epitaxy inside an emitter opening and an undercut formed under the extrinsic base polysilicon layer (e.g., see U.S. Pat. No. 5,494,836, Imai, Feb. 27, 1996 (incorporated herein by reference), U.S. Pat. No. 5,506,427, Imai, Apr. 9, 1996 (incorporated herein by reference) and U.S. Pat. No. 5,962,880, Oda et al., Oct. 5, 1999 (incorporated herein by reference). Self-alignment of the extrinsic base is achieved with the epitaxial growth inside the undercut and special techniques are required to ensure a good link-up contact between the intrinsic base and the extrinsic base. See also U.S. Pat. No. 6,869,852, Joseph et al., Mar. 22, 2005 (incorporated herein by reference) and U.S. Patent Pub. No. US 2005/0048735, Khater et al., Mar. 3, 2005 (incorporated herein by reference), which also describe methods of forming a transistor with a self-aligned raised extrinsic base. Although there are known methods of fabricating a transistor with a self-aligned raised extrinsic base to reduce base resistance, these known methods often have process and manufacturing complexities. Thus, there is a need in the art for a simple fabrication method to manufacture a bipolar transistor with a self-aligned raised extrinsic base.